vga or dvi-i port companion circuit CM2009-05CP ?2010 scillc. all rights reserved. publication order number: april 2010 rev. p2 CM2009-05CP/d advance information features ? includes esd protection, level-shifting, buffering and sync impedance matching ? vesa vsis version 1 revision 2 compatible interface ? supports both source and sink devices ? supports optional navi signaling requirements ? seven channels of esd protection for all vga port connector pins meeting iec-61000-4-2 level 4 esd requirements ( 8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines, 3pf maximum ? schmitt-triggered input buffers for hsync and vsync lines ? bi-directional level shifting n-channel fets provided for ddc_clk & ddc_data channels ? backdrive protection on all lines ? rohs-compliant, lead-free finishing in a 14- bump, 5x4x5, 0.4mm chip scale package (csp) applications ? monitors ? video graphics controllers embedded in pcs ? graphics adapter cards ? set-top boxes product description t he CM2009-05CP connects between the vga or dvi-i port connector and the internal analog or digital flat panel controller logic. it can also be used for source devices such as a set-top box. the cm2009- 05cp incorporates esd protection for all signals, level shifting for the ddc signals and buffering for the sync signals. esd protection for the video, ddc and sync lines is implemented with low-capacitance current steering diodes. all connector interface pins are designed to safely handle the high current spikes specified by iec- 61000-4-2 level 4 ( 8kv contact discharge). the esd protection for the ddc, sync and video signal pins is designed to prevent "back current" when the device is powered down while connected to a video source or a video sink that is powered up. positive supply rails are provided for the video / sync signals and ddc si gnals to facilitate interfacing with low voltage video controller ics and microcontrollers to provide design flexibility in multi- supply-voltage environments. two schmitt-triggered non-inverting buffers redrive and condition the hsync and vsync signals from the video connector (sync1, sync2). these buffers accept vesa vsis compliant ttl input signals and convert them to cmos output levels that swing between ground and v cc. two n-channel mosfets provide the level shifting function required when the ddc controller or edid eeprom is operated at a lower supply voltage than the monitor. the gate terminals for these mosfets should be connected to the supply rail (typically 3.3v, 2.5v etc.) that supplies power to the transceivers of the ddc controller.
CM2009-05CP rev. p2 | page 2 of 8 | www.onsemi.com
CM2009-05CP rev. p2 | page 3 of 8 | www.onsemi.com pin descriptions lead(s) name description a1 gnd ground reference supply pin. a2 video_1 video signal esd protection channel. this pin is typically tied one of the video lines between the controller device and the video connector. a3 video_2 video signal esd protection channel. this pin is typically tied one of the video lines between the controller device and the video connector. a4 video_3 video signal esd protection channel. this pin is typically tied one of the video lines between the controller device and the video connector. a5 v cc this is a supply input for the sync_1 and syn c_2 level shifters, video protection and the ddc circuits. b1 ddc_out1 ddc signal output. connects to the ddc logic. b2 ddc_out2 ddc signal output. connects to the ddc logic. b3 sync_out1 sync signal buffer output. connects to the monitor sync logic. 1 b4 sync_out2 sync signal buffer output. connects to the monitor sync logic. 1 c1 ddc_in1 ddc signal input. connects to the video connector side of one of the ddc lines. c2 ddc_in2 ddc signal input. connects to the video connector side of one of the ddc lines. c3 lv_en disables the sync buffer outputs when low. c4 sync_in1 sync signal buffer input. connects to the video connector side of one of the sync lines. 2 c5 sync_in2 sync signal buffer input. connects to the video connector side of one of the sync lines. 2 note 1: can also be connected to the vga connector side if used for a source device. note 2: can also be used to connect to the video chip sync logic if it is used for a source device. ordering information part numbering information bumps package ordering part number 1 part marking 14 csp CM2009-05CP tj note 1: parts are shipped in tape and reel form.
CM2009-05CP rev. p2 | page 4 of 8 | www.onsemi.com specifications absolute maximum ratings parameter rating units v cc supply voltage inputs [gnd - 0.5] to +6.0 v dc voltage at inputs video_1, video_2, video_3 ddc_in1, ddc_in2 ddc_out1, ddc_out2 sync_in1, sync_in2, lv_en [gnd - 0.5] to [v cc + 0.5] [gnd - 0.5] to 6.0 [gnd - 0.5] to 6.0 [gnd - 0.5] to [v cc + 0.5] v v v v operating temperature range -40 to +85 c storage temperature range -40 to +150 c package power rating (t a =25c) 500 mw standard operating conditions parameter rating units operating temperature range -40 to +85 c v cc 5 v
CM2009-05CP rev. p2 | page 5 of 8 | www.onsemi.com electrical operating characteristics (see note 1) symbol parameter conditions min typ max units v cc = 5v; sync inputs at gnd or v cc ; sync outputs unloaded, ddc_in and ddc_out floating 1.0 ma i cc v cc supply current v cc = 5v; sync inputs at 3.0v; sync outputs unloaded, ddc_in and ddc_out floating 2.0 ma v f esd diode forward voltage i f = 10ma 1.1 v v ih logic high input voltage v cc = 5.0v; note 2 2.0 v v il logic low input voltage v cc = 5.0v; note 2 0.55 v v hys hysteresis voltage v cc = 5.0v; note 2 450 mv v oh logic high output voltage i oh = 0ma, v cc = 5.0v; note 2 4.0 v v ol logic low output voltage i ol = 0ma, v cc = 5.0v; note 2 0.15 v r out sync driver output resistance v cc = 5.0v; sync inputs at gnd or 3.0v 65 input current video inputs v cc = 5.0v; v in = v cc or gnd 10 a i in sync_in1, sync_in2 inputs v cc = 5.0v; v in = v cc or gnd 10 a (lv_en - v ddc_in ) 0.4v; v ddc_out = lv_en 10 a i off level shifting n-mosfet "off" state leakage current (lv_en - v ddc_out ) 0.4v; v ddc_in = lv_en 10 a i backdrive current conducted from input pins when vcc is powered down. v cc < v input_pin 10 a v on voltage drop across level-shifting n-mosfet when "on" lv_en = 2.5v; v s = gnd; i ds = 3ma 0.18 v v cc = 5.0v; v in = 2.5v; f = 1mhz 3 pf c in_vid video input capacitance v cc = 2.5v; v in = 1.25v; f = 1mhz 3.5 pf t plh sync driver l => h propagation delay c l = 50pf; v cc = 5.0v; input t r and t f 5ns 12 ns t phl sync driver h => l propagation delay c l = 50pf; v cc = 5.0v; input t r and t f 5ns 12 ns t r, t f sync driver output rise & fall times v cc = 5v 7 ns v esd esd withstand voltage v cc = 5v; note 3 8 kv note 1: all parameters specified over standard ope rating conditions unless otherwise noted. note 2: these parameters apply only to th e sync drivers. note that r out = r t + r buffer. note 3: per the iec-61000-4-2 international esd standar d, level 4 contact discharge method. v cc must be bypassed to gnd via a low impedance ground plane with a 0.22 f, low inductance, chip ceramic capa citor at each supply pin. esd pulse is applied between the applicable pins and gnd. esd pulses can be positive or negative with respect to gnd.
CM2009-05CP rev. p2 | page 6 of 8 | www.onsemi.com application information figure 1. typical application connection diagram notes: 1 the CM2009-05CP should be placed as close to the vga or dvi-i connector as possible. 2 the esd protection channels video _1, video_2, video_3 may be used in terchangeably between the r, g, b signals. 3 if differential video signal routing is used, the red, blue, and green signal lines should be terminated with external 37.5 ohm resistors. 4 "vf" are external video filters for the rgb signals. 5 supply bypass capacitors c1 and c2 must be placed immediately adjacent to the corresponding vcc pins. connections to the vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best esd protection. 6 the bypass capacitor for the byp pin has been omitted in this diagram. this results in a reduction in the maximum esd withstand voltage at the ddc_out pins from 8kv to 2kv. if 8kv esd protection is required, a 0.22 f ceramic bypass capacitor should be connected between byp and ground. 7 the sync buffers may be used interchangeably between hsync and vsync. 8 the emi filters at the sync_out and ddc_o ut pins (c5 to c12, and ferrite be ads fb1 to fb4) are for reference only. the component values and f ilter configuration may be c hanged to suit the application. 9 the ddc level shifters ddc_in, ddc_out, may be used interchangeably between ddca_clk and ddca_data. 10 r1, r2 are optional. they may be used, if required, to pull the ddc_clk and ddc_data lines to vcc_5v when no monitor is connected to the vga connector. if used, it s hould be noted that "back current" may flow between the ddc pins and vcc_5v via these resistors when vcc_5v is powered down.
CM2009-05CP rev. p2 | page 7 of 8 | www.onsemi.com mechanical specification package specification the CM2009-05CP is supplied in 14-bump, 5-4-5 chip scale package (csp). package dimensions package custom csp bumps 14 millimeters inches dim min nom max min nom max a1 1.955 2.000 2.045 0.077 0 0.0787 0.0805 a2 1.055 1.100 1.145 0.041 5 0.0433 0.0451 b1 0.395 0.400 0.405 0.015 6 0.0157 0.0159 b2 0.195 0.200 0.205 0.007 7 0.0079 0.0081 b3 0.342 0.347 0.352 0.013 5 0.0137 0.0139 b4 0.342 0.347 0.352 0.013 5 0.0137 0.0139 c1 0.150 0.200 0.250 0.005 9 0.0079 0.0098 c2 0.153 0.203 0.253 0.006 0 0.0080 0.0100 d1 0.530 0.580 0.630 0.020 9 0.0228 0.0248 d2 0.363 0.391 0.419 0.014 3 0.0154 0.0165 # per tape and reel 3500 controlling dimension: millimeters figure 2. package dimensions for CM2009-05CP 14-bump chip scale package
CM2009-05CP rev. p2 | page 8 of 8 | www.onsemi.com csp tape and reel specifications part number chip size (mm) pocket size (mm) b 0 x a 0 x k 0 tape width w reel diameter qty per reel p 0 p 1 CM2009-05CP 2.00 x 1.10 x 0.58 2.20 x 1.22 x 0.73 8mm 178mm (7") 3500 4mm 4mm + + + figure 3. tape and reel mechanical data on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or spec ifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not de signed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reason able attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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